This application claims the priority benefit of Taiwan application serial no. 91108517, filed Apr. 25, 2002.
1. Field of the Invention
present invention relates to a fabrication method for a memory device. More particularly, the present invention relates to a method that uses a raised bit line to improve the memory characteristic of a memory device.
2. Description of Related Art
A memory device, apparently, is a semiconductor device used in storing information or data. For the storage of digital information, memory capacity is normally described in terms of xe2x80x9cbitxe2x80x9d. Each unit in a memory device for storing information is known as a xe2x80x9ccellxe2x80x9d. The exact location of each memory cell in millions of memory cells is known as the xe2x80x9caddressxe2x80x9d. The memory cells in a memory device are arranged in an array, where each row along with each column constitutes a specific memory address. Memory cells of a same row or of a same column are connected together by a common conductive line.
As shown in FIG. 1, FIG. 1 illustrates a cross-sectional view of a conventional memory device.
Referring to FIG. 1, according to the conventional fabrication method for a memory device, a gate structure 108 is formed on a substrate 100, wherein the gate structure includes a gate conductive layer 104 and a gate oxide layer 102. A buried bit line 112 is then formed in the substrate 100 beside the gate structure 108. Thereafter, an insulation layer 116 is formed on the substrate 100 above the buried bit line 112. The insulation layer 116 is used to isolate the gate structures 108. A word line 118 is further formed on the substrate 100 to electrically connect a row of gate structures 108.
As memory devices continue to reduce in size along with the increase in the integration of integrated circuits, the dimension of the buried bit line needs to be reduced correspondingly. Consequently, the current flow in a memory cell becomes small and the bit line becomes overloaded. If by increasing the junction depth of the bit line to resolve the problem of the increase of the bit line resistance, not only short channel effect may develop, the problem of punch-through leakage may result. If a high dopant concentration is used to form a shallow junction bit line in order to prevent the short channel effect and the punch-through leakage problem due to a deep junction depth, the problem of overloading the bit line remains unresolved due to the limitation of solid phase solubility.
Accordingly, the present invention provides a fabrication method for a memory device in which the resistance of the bit line is lower.
The present invention also provides a fabrication method for a memory device, wherein the buried bit line can have a shallow junction to prevent the problems of short channel effect and punch-through leakage.
The present invention further provides a fabrication method for a memory device. The method comprises forming a pad oxide layer on a substrate. A silicon nitride mask layer is further formed on the pad oxide layer, wherein the silicon nitride mask layer exposes a portion of the pad oxide layer. Thereafter, an ion implantation process is performed to form a buried bit line in the part of the substrate not covered by silicon nitride mask layer. The present invention further comprises forming a pocket doped region beside the side of the buried bit line. A raised bit line is then formed on the pad oxide layer that is above the buried bit line. Forming the raised bit line includes using the pad oxide layer as a seed layer and then forming a selective epitaxy layer as the raised bit line on the exposed pad oxide layer. Thereafter, the mask layer and the pad oxide layer are removed. A conformal oxide layer is then formed on the substrate and on the raised bit line, followed by forming a word line on the gate oxide layer.
Since the bit line of the memory device of the present invention is formed by the buried bit line and the raised bit line, the resistance of the bit line is effectively reduced to prevent overloading the bit line.
Further, the memory device formed according to the present invention includes a raised bit line. The junction of the buried bit line can be shallow to prevent the short channel effect and the problem of punch-through leakage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.